The present invention relates generally to electronic packaging, and more particularly, to an interconnect structure for mounting a semiconductor chip and method of forming same.
As the demand grows in the industry for miniaturized high performance semiconductor packages, the need to manufacture a reliable high density interconnect structure for mounting semiconductors becomes increasingly important. Producing an interconnect structure having the largest number of chip connections over the smallest possible area is an important objective. It is also important to produce a structure capable of providing adequate wiring capabilities to take advantage of the high density connections.
FIG. 1 shows a much enlarged view, in elevation, of a prior art semiconductor chip carrier 10. The chip carrier 10 includes a substrate 12, a plurality of plated through holes 14, and a layer of conductive material 16 positioned on the side wall of each of the plated through holes and on portions of the surface of substrate 12. The conductive material 16 on portions of the surface of substrate 12 form connection pads 18. A first dielectric layer 20 is positioned on the exposed surface of substrate 12 and on portions of the layer of conductive material 16. The first dielectric layer 20 includes interconnection contact areas 22, which facilitate electrical connection of semiconductor chips (not shown), through interconnections (also not shown), to connection pads 18 of the plurality of plated through holes 14.
FIG. 2 shows a top view of a portion of semiconductor chip carrier 10. The connection pads 18 are dogbone shaped and consume a large portion of the surface area on the carrier 10. This is because each interconnection contact area 22, the area upon which the semiconductor chip interconnection is mounted, is offset from its corresponding plated through hole 14. As a result, the density of plated through holes 14 and interconnections between the semiconductor chip and interconnect contact areas 22 for each carrier 10 is limited.
Additionally, due to differences in the coefficient of thermal expansion between the semiconductor chip carrier, the chips and the interconnections therebetween, internal stresses develop within the semiconductor package during thermal cycling, which may eventually lead to interconnection or device failure.
As a result, there exists a need in the industry for a more reliable, compact interconnect structure which overcomes the disadvantages of known structures.
Accordingly, it is an object of this invention to enhance the art of electronic packaging.
Another object of this invention is to provide an interconnect structure having highly dense spacing between plated through holes and semiconductor chip interconnection contact areas and a method of forming the same.
Yet another object of this invention is to provide an interconnection structure having highly dense spacing between plated through holes and semiconductor chip interconnection contact areas, the interconnection structure including a metal layer between the first and second opposing surfaces of the interconnection structure and first and second non-conductive layers positioned, respectively between the first opposing surface and the metal layer and between the second opposing surface and the metal layer.
Still yet another object of this invention is to provide such a method and structure that improves reliability and electrical performance.
According to one aspect of the invention, there is provided an interconnect structure comprising a substrate having first and second opposing surfaces and at least one internal side wall defining a through hole within the substrate extending from the first opposing surface to the second opposing surface, a first conductive material positioned on the at least one internal side wall of the substrate, a first conductive layer positioned on a portion of the first surface of the substrate, the first conductive layer having a first layer portion positioned over the through hole and electrically connected to the first conductive material on the internal side wall of the substrate. A second conductive layer is positioned on a portion of the second surface of the substrate, the second conductive layer having a first layer portion positioned over the through hole and electrically connected to the first conductive material on the internal side wall of the substrate, a first dielectric layer positioned on the first conductive layer and the first opposing surface of substrate and having at least one internal side wall defining an aperture in the first dielectric layer, and a second conductive material positioned on the internal side wall of the first dielectric layer and including a portion of the second conductive material positioned on and electrically connected to the first layer portion of the first conductive layer.
According to another aspect of the invention there is provided a method of forming an interconnect structure comprising the steps of providing a substrate having first and second opposing surfaces and at least one internal side wall defining a through hole within the substrate extending from the first opposing surface to the second opposing surface, positioning a first conductive material on the at least one internal side wall of the substrate, positioning a first conductive layer on a portion of the first surface of the substrate, the first conductive layer having a first layer portion positioned over the through hole and electrically connected to the first conductive material on the internal side wall of the substrate. The method includes positioning a second conductive layer on a portion of the second surface of the substrate, the second conductive layer having a first layer portion positioned over the through hole and electrically connected to the first conductive material on internal side wall of substrate, positioning a first dielectric layer on the first conductive layer and the first opposing surface of the substrate and having at least one internal side wall defining an aperture in the first dielectric layer, and positioning a second conductive material on the internal side wall of the first dielectric layer and including a portion of the second conductive material positioned on and electrically connected to the first layer portion of the first conductive layer.
According to yet another aspect of the invention, there is provided an interconnect structure comprising, a substrate having first and second opposing surfaces and at least one internal side wall defining a through hole within the substrate extending from the first opposing surface to the second opposing surface, wherein the substrate includes a metal layer between the first and second opposing surfaces and first and second non-conductive layers positioned, respectively, between the first opposing surface and the metal layer and between the second opposing surface and the metal layer, a first conductive material positioned on the at least one internal side wall of the substrate, a first conductive layer positioned on a portion of the first surface of the substrate, the first conductive layer having a first layer portion positioned over the through hole and electrically connected to the first conductive material on the internal side wall of the substrate. A second conductive layer is positioned on a portion of the second surface of the substrate, the second conductive layer having a first layer portion positioned over the through hole and electrically connected to the first conductive material on the internal side wall of the substrate, a first dielectric layer positioned on the first conductive layer and the first opposing surface of the substrate and having at least one internal side wall defining an aperture in the first dielectric layer, and a second conductive material positioned on the internal side wall of the first dielectric layer and including a portion of the second conductive material positioned on and electrically connected to the first layer portion of the first conductive layer.
The foregoing and other features of the invention will be apparent from the following more particular description of the embodiments of the invention.